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Six frames, more than 100 inspection items, ensure PCB design no more mistakes | YMSPCB

Six frames, more than 100 inspection items, to ensure that PCB design is no longer wrong, Chinese PCB board manufacturers for you to sort out the following contents;

I. Data input stage

1. Whether the information received on the process is complete (including: schematic diagram, *. BRD file, material list, PCB design instructions, PCB design or change requirements, standardization requirements, process design instructions)

2. Confirm PCB template is up to date

3. Confirm the correct position of the template positioning device

4. Clear PCB design instructions, PCB design or change requirements and standardization requirements

5. Confirm that the prohibited placement of devices and wiring areas on the outline drawing have been reflected in the PCB template

6. Compare the outline drawing, confirm the correct size and tolerance of PCB, and the correct definition of metallized hole and nonmetallic hole

7. After confirming the accuracy of PCB template, it is better to lock the structure file, so as to avoid misoperation and moving position

II. Post-layout inspection stage

A. Device inspection

8. Confirm whether all device packages are consistent with the company’s unified library and whether the packaging library has been updated (use viewlog to check the running results). If not, Update Symbols

9. Mother board and child board, single board and back board, confirm the signal correspondence, position correspondence, connector direction and screen mark are correct, and the child board has anti-misplacement measures, the device on the child board and mother board should not produce interference

10. The components are 100% placed or not

11. Open the place-bound of the TOP and BOTTOM layers of the device and check whether DRC caused by overlap is allowed

12. Is Mark sufficient and necessary

13. Heavier components should be placed near PCB support points or supporting edges to reduce PCB warping

14. It is better to lock the structure-related devices after they are installed, so as to prevent misoperation and moving position

15. Within the range of 5mm around the crimp socket, no element whose height exceeds the height of the crimp socket shall be allowed on the front side, and no element or solder joint shall be allowed on the back side

16. Confirm whether the device layout meets the process requirements (focus on BGA, PLCC, patch socket)

17. For components of metal shell, pay special attention not to touch with other components and leave enough space

18. Place interface-related devices as close to the interface as possible, and place backboard bus drivers as close to the backboard connector as possible

19. Has the CHIP device on wave soldering surface been converted into wave soldering package?

20. Whether there are more than 50 manual welding spots

21. Horizontal mounting should be considered for axial mounting of higher components on PCB.Set aside room to lie down.And consider the fixed way, such as crystal vibration fixed pad

22. For components requiring the use of fins, make sure there is enough space between them and other components, and pay attention to the height of major components within the range of fins

B. Function check

23. Whether the digital circuit and analog circuit components of the digital-analog hybrid board have been separated and whether the signal flow is reasonable

24. A/D converter placed across the analog and digital partition.

25. Whether the clock device layout is reasonable

26. Is the layout of high-speed signal device reasonable

27. Whether the end device has been properly placed (source matching series resistance should be placed in the driver end of the signal;Intermediate matching string resistance in the middle position;Terminal matching string resistance should be placed at the receiving end of the signal)

28. Whether the number and position of decoupling capacitors of IC devices are reasonable

29. The signal line takes the plane of different levels as the reference plane. When crossing the dividing area of the plane, whether the connection capacitance between the reference planes is close to the wiring area of the signal.

30. Whether the layout of the protection circuit is reasonable and conducive to segmentation

31. Whether the fuse of the single board power supply is placed near the connector and there is no circuit element in front

32. Confirm that the strong signal and the weak signal (power difference of 30dB) are arranged separately

33. Whether devices that may affect EMC experiments are placed in accordance with design guidelines or reference to successful experience.For example: the reset circuit of the panel should be slightly close to the reset button

C. Fever

Heat sensitive components (including liquid dielectric capacitance and crystal oscillator) should be kept away from high-power components, radiators and other heat sources

35. Whether the layout meets the requirements of thermal design, heat dissipation channel (to be executed according to the process design document)

D. The power

36. Whether the IC power supply is too far from IC

37. Is the layout of LDO and its surrounding circuits reasonable

38. Is the layout of the circuit around the module power supply reasonable

39. Is the overall layout of the power supply reasonable

E. Rule setting

40. Whether all the simulation constraints have been correctly added to the Constraint Manager

41. Whether the physical and electrical rules are set correctly (note the constraint Settings of the power network and the ground network)

42. Whether the spacing Settings of Test Via and Test Pin are sufficient

43. Whether the thickness and scheme of the lamination meet the design and processing requirements

44. Whether all differential line impedances required by characteristic impedances have been calculated and controlled by rules

III. Post-wiring inspection stage


45.Whether the wiring of digital circuit and analog circuit has been separated, and whether the signal flow is reasonable

46. If A/D, D/A and similar circuits divide the ground, does the signal line between the circuits go through the bridge between the two places (except the difference line)?

47. Signal lines that must span the gap between dividing power sources should refer to the complete ground plane.

48. If the stratigraphic design is adopted without partition, digital signals and analog signals shall be arranged in partition.

G. Clock and high-speed section

49.Whether the impedance layers of the high-speed signal line are consistent

50. Are high-speed differential signal lines and similar signal lines equally long, symmetrical and parallel to each other?

51. Make sure the clock line goes as far as possible through the inner layer

52. Confirm whether clock lines, high-speed lines, reset lines and other strong radiation or sensitive lines have been wired according to the 3W principle as far as possible

53. Is there no forking test point on clock, interrupt, reset signal, 100 MB/gigabit Ethernet, high-speed signal?

54.Is it possible that 10H (H is the height of signal line from reference plane) between LVDS and TTL/CMOS signals?

55. Do clock lines and high-speed signal lines avoid crossing dense through-hole through-hole areas or between device pins?

56. Whether the clock line has met the requirements (SI constraint) (whether the clock signal routing should be less perforated, shorter, continuous in the reference plane, and the main reference plane should be GND as far as possible;If GND main reference plane is changed during laming, GND over-hole is within the range of 200mil from the over-hole.) if different levels of main reference plane are changed during laming, is there any decoupling capacitor within the range of 200mil from the over-hole?

57. Whether differential pairs, high-speed signal lines and various BUS have met the requirements of SI constraint

H. Mc and reliability

58. For crystal oscillator, should a layer be laid under it?Are signal lines prevented from crossing device pins?For high-speed sensitive devices, are signal lines prevented from crossing from pin to pin?

59. There should be no acute Angle or right Angle on the track of single board signal (generally, continuous turning is at an Angle of 135 degrees, and the radiofrequency signal line should adopt circular arc or calculated Angle cutting copper foil).

60. For double panels, check whether the high-speed signal line is wired close to its backflow ground;For multiple layers, check that the high-speed signal line is aligned as closely as possible to the ground plane

61. For the signal routing of two adjacent layers, try to be vertical

62.Avoid signal line crossing from power module, common mode inductor, transformer and filter

63. Try to avoid long distance parallel routing of high-speed signals on the same layer

64. Is there any shielding through hole in the dividing edge of the plate edge including digital, analog and protective ground?Are multiple ground planes connected by holes?Is the hole crossing distance less than 1/20 of the signal wavelength of the highest frequency?

65. Is the signal routing of the surge suppressor short and thick on the surface?

66. Confirm that there are no isolated islands in the power supply and formation, no too large grooves, no longer ground plane cracks caused by too large or dense over-holes in the through-hole isolation disc, no slender strips or narrow channels

67. Are ground holes placed where there are many signal lines spanning layers (at least two ground planes are required)?

I. Power and ground

68. If there is a division in the power/ground plane, try to avoid crossing high-speed signals on the divided reference plane.

69.Make sure the power supply and ground can carry enough current.(estimation method: 1A/mm wire width at 1oz thickness of outer copper layer, 0.5A/mm wire width of inner layer, double short-line current)

70.Whether the power supply with special requirements meets the requirements of voltage drop

71. In order to reduce the radiation effect at the edge of the plane, the 20H principle should be satisfied between the power layer and the stratum as far as possible.The more indented the power layer is, the better.

72. If there is a ground division, does the divided ground not constitute a loop?

73. Are different power surfaces of adjacent layers avoided from overlapping?

74. Is the isolation of protected land, -48v land and GND greater than 2mm?

75. Is the -48v signal just backflowing to the -48v signal and not to the other places?If not, please explain the reason in the remarks column.

76. Shall there be a protective floor of 10~20mm near the connector panel and connect the layers with double row staggered holes?

77. Does the distance between the power line and other signal lines meet the safety requirements?

J. Forbidden area

78. There shall be no wiring, copper skin and over-hole that may cause short-circuit under metal shell devices and heat dissipation devices

79. Install screws or washers without wiring, copper, or through holes that may cause a short circuit

80. Is there any routing in the reserved position in the design requirements

81. The distance between the inner layer of the non-metallic holes from the line and copper foil should be greater than 0.5mm (20mil), the outer layer 0.3mm (12mil), the distance between the inner layer of the single-plate wrench shaft hole from the line and copper foil should be greater than 2mm (80mil)

82. Copper sheet and wire to plate edge is recommended to be greater than 2mm and minimum 0.5mm

83. The inner layer layer copper skin to the plate edge 1 ~ 2 mm, the minimum is 0.5mm

K. Wire out of pad

84. For CHIP elements installed on two pads (package 0805 and below), such as resistors and capacitors, the printed wires connected to the pads should be drawn symmetrically from the center of the pads, and the printed wires connected to the pads should have the same width. This provision may be ignored for the lead wires with line width less than 0.3mm(12mil)

85. For a pad connected with a wide printed line, it is better to pass through a narrow printed line in the middle.(0805 and below)

86. The line shall be drawn from both ends of the pads of SOIC, PLCC, QFP, SOT and other devices as far as possible

L. Screen printing

87. Whether the device bit number is missed, and whether the position can correctly identify the device

88. Whether the device bit number meets the company’s standard requirements

89.Verify the pin ordering of the device, pin 1 mark, device polarity mark and connector orientation mark

90. Whether the direction marks of the board board and the board board are corresponding

91. Whether the back plate correctly identifies the slot name, slot number, port name and jacket direction

92. Confirm whether the addition of silk screen printing required by design is correct

93. Confirm that anti-static and rf board identification has been placed (rf board is used)

M. Code/bar code

94. Confirm that PCB code is correct and in accordance with company specifications

95. Confirm that the PCB coding position and layer of the single board are correct (it should be on the upper left of side A, the silk-screen layer).

96. Confirm that the PCB coding position and layer of the back plate are correct (it should be on the upper right of B with outer copper foil).

97. Confirm barcode laser printing white silk screen marking area

98. Confirm that there is no connection below the bar code box and that the conducting hole is greater than 0.5mm

99. Confirm that there shall be no device with a height of more than 25mm outside the white screen printing area of barcode

N. A hole

100. On the reflow surface, through hole cannot be designed on the pad.(the spacing between the holes and the pads should be greater than 0.5mm (20mil) for the normal window opening and greater than 0.1mm (4mil) for the green-oil covered holes.

101. The over-hole arrangement should not be too close to avoid causing large-scale fracture of power supply and ground plane

102. The diameter of the hole should be no less than 1/10 of the thickness of the plate

O. Process

103.Whether the device layout rate is 100%, whether the layout rate is 100% (if not 100%, it needs to be explained in the note)

104.Whether the line was adjusted to the minimum, and it was confirmed one by one for the reserved line.

105. Has the process problem feedback from the process department been checked carefully

P.Large area of copper foil

106. For large-area copper foil on Top and bottom, if there is no special need, use copper mesh [inclined mesh for single plate, orthogonal mesh for back plate, line width of 0.3mm (12 mil), spacing of 0.5mm (20mil)

107. Component pads in large area of copper foil area should be designed as flowered pads to avoid false welding;When there is a current requirement, consider widening the bead of the splint, and then consider full connection

108. When distributing copper in a large area, dead copper without network connection should be avoided as much as possible.

109. Large area copper foil also need to pay attention to whether there is illegal wire, unreported DRC

Q. Test points

110. Whether the test points of various power sources and ground are sufficient (at least one test point for each 2A current)

111.Verify that networks without test points are validated to be streamlined

112. Verify that test points are not set on plug-ins that are not installed in production

113. Test Via, Test whether Pin has been fixed (applicable to changing board without changing needle bed)


114. Test via and Test pin Spacing Rule should be set to the recommended distance first, check for DRC, if there is still DRC, check for DRC with the minimum distance setting

115. Turn the constraint on to turn it on, update DRC to see if there are any unallowed errors in DRC

116. Confirm that the DRC has been adjusted to a minimum, one by one if the DRC cannot be eliminated;

S. Optical registration point

117. Confirm that there is an optical positioning symbol on the PCB surface with mounting element

118. Confirm optical positioning symbol unpressed wire (silk screen and copper foil wiring)

119. The background of optical positioning point should be the same. Make sure that the center of the entire plate is ≥5mm away from the edge with the optical point

120. Confirm that the coordinate value has been assigned to the optical positioning reference symbol of the whole plate (it is recommended to place the optical positioning reference symbol in the form of device) and it is an integral value in millimeters.

121. For IC devices with pin center distance <0.5mm and BGA devices with center distance less than 0.8 mm (31 mil), an optical positioning point shall be set near the diagonal of the element

T. Welding resistance inspection

122. Confirm that all pads with special requirements are properly windowed (pay particular attention to the design requirements of hardware)

123. Whether the through hole under BGA should be treated as oil cover plug hole

124. In addition to testing the hole, whether the hole has been made to open a small window or cover the oil plug hole

125. Does the window opening at the optical anchor point avoid copper and wire exposure

126. Power supply chip, crystal oscillator and other devices that need copper skin heat dissipation or earthing shielding should have copper skin and properly open Windows.Devices fixed by solder should have green oil to block large area diffusion of solder

V.Processing documents

U. Drilling figure

127. Notes PCB board thickness, number of layers, screen printing color, warping, and other technical specifications are correct

128. Whether the lamination name, lamination sequence, medium thickness and copper foil thickness of the lamination diagram are correct;Whether impedance control is required and the description is accurate.Whether the layer name of the laminate map is consistent with its light-painted file name

129. Close the Repeat code in the setting table, and the drilling precision should be set to 2-5

130. Whether the hole table and borehole file are up to date (when the hole is changed, it must be regenerated)

131. Whether there is abnormal aperture in the hole table, and whether the aperture of pressure joint is correct;Whether the aperture tolerance is marked correctly

132. Is the through-hole of fortress hole listed separately marked with "filled vias"?

V. Light painting

133. The output of optical drawing file shall adopt RS274X format as far as possible, and the accuracy shall be set at 5:5

134. Has art_aper. TXT been updated (274X is not needed)

135. Whether there is any abnormal report in the log file of the output light drawing file

136. Edge and island identification of negative layer

137. Use the light drawing inspection tool to check whether the light drawing file is consistent with PCB (comparison tool should be used to compare the board)

W. Complete set of documents

138.PCB file: product model _ specification _ single board code _ version number. BRD

139.Backing board design document: product model _ specification _ single board code _ version number -CB[-t /B].brd

140.PCB processing file: PCB code. Zip (including light drawing file, aperture meter, drilling file and ncdrill-log of each layer;The assembling board shall also have the assembling file *.dxf provided by the process, and the backing board shall be attached with the liner file: PCB code -cb [-t /B].zip (including drill.art, *.drl, ncdrill.log)

141. Process design document: product model _ specification _ single board code _ version number – gy.doc

142.SMT coordinate file: product model _ specification _ single board code _ version number – smt.txt, (when output coordinate file, confirm to select Body center, only select Symbol origin when confirming that the origin of all SMD device library is device center)

143.PCB board structure file: product model _ specification _ single board code _ version number – McAd.zip (including.DXF and.EMN files provided by the structural engineer)

144.TEST file: product model _ specification _ single board code _ version number – test.zip (contains the coordinate file of testprep. Log and untest.lst or *.drl TEST point)

145. Archived drawing file: product model specification – single board name – version number. PDF, (including: cover, home page, silk-screen printing of each layer, wiring of each layer, drilling drawing, backboard including liner drawing)

VI. Standardization

146. Confirm the correct information of cover and home page

147. Confirm that the drawing number (corresponding to the sequence of PCB layers) is correct

148. Confirm that the PCB code on the drawing frame is correct

 China Yongmingsheng is a high-tech enterprise specialized in manufacturing and selling flexible Board,Rigid+Flex,Metal core PCB.Since its establishment, YMS has been committed to building the manufacturer with the best quality and fastest delivery in PCB industry.

Post time: Aug-09-2019
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